Flash memories are commonly applicable to mass storage subsystems for electronic devices employed in mobile communications, game sets, and so on. Such subsystems are usually implemented as either removable memory cards that can be inserted into multiple host systems or as non-movable embedded storage within the host systems. In both implementations, the subsystem includes one or more flash devices and often a subsystem controller.
Flash memories are composed of one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data. Therefore, flash memories do not require power to retain the data programmed therein. Once programmed however, a cell must be erased before it can be reprogrammed with a new data value. These arrays of cells are partitioned into groups to provide for efficient implementation of read, program and erase functions. The typical flash memory architecture for mass storage arranges large groups of cells into erasable blocks. Each block is further partitioned into one or more addressable sectors that are the basic unit for read and program functions.
Flash memories basically have their own functional operations of reading, writing (or programming), and erasing. Especially, flash memories additionally extend their facilities to practice a page copy operation (or a copy-back operation). The page copy operation is to transcribe data stored in a page assigned to a specific address to another page assigned to another address. During the page copy, data stored in a page (i.e., a source page) of a specific address are transferred to a page buffer and then the data stored in the page buffer are written into another page (i.e., a target page) assigned to another address by means of a programming process without reading the data out of the flash memory. The page copy function eliminates the need to read-out data to be written and to load data to be written from the external source of the flash memory, which is advantageous to enhancing systemic data rates associated with the subsystem controller.
In the meantime, an over-writing function is not available in the flash memory. Thus, data can be written only into a page that is sustained in an erase state. The page to be written with data must be erased prior to a write (or programming) operation. However, as it is usual for an erase time of the flash memory to take several milli-seconds, every erasing step before writing causes a speed performance to be degraded. By that reason, a memory controller manages the flag memory, such that after data of a specific page is transcribed into an erased page, a memory field including the original data is erased by the block (or the sector) in a surplus time during its operational term.
FIG. 1 illustrates the general scheme of a copy-back operation. Referring to FIG. 1, a memory controller 10 supplies control signals CTRL, command signals CMD, and address signals ADDR to a flash memory 20 and exchanges data signals DIO with the flash memory 20. The flash memory 20 includes a cell array 21 for storing the data and a page buffer block 22 for registering the data to be accessible in a copy-back operation.
The cell array 21 is composed of a plurality of pages each formed of memory cells sharing a single wordline. While a single page as a unit for reading and writing data is designed to store 512 B (Bytes) of data normally at present, the storage capacity of the page is being expanded up to 2 KB in the future.
A copy-back operation is divided into an operation of transcribing data from a source page into the page buffer block 22 and an operation of writing the data into a target page D from the page buffer block 22.
When a copy command and an address assigned to the source page S are provided by the memory controller 10, data Unit-K stored in the source page S is copied into the page buffer block 22. When a copy-back command and an address assigned to the target page D are provided by the controller 10, the data Unit-K stored in the page buffer block 22 is transferred to the target page D.
Recently with the trends of managing the unit pages in a consolidated page in order to enhance operational speeds and to reduce chip sizes, a plurality of unit pages are contemporaneously copied into the page buffer block and transferred into the target pages at the same time.
Such a lumped copy-back operation may be practicable when the memory controller 10 can manage the data (e.g., Unit K-3 through Unit K) stored in a plurality of unit pages at the same time. However, if the memory controller 10 is configured to manage the unit page only, it may cause an unnecessary copy-back result for a unit page that is not to be copied.
For instance, although a part of unit pages data stored in the page buffer block is in need of being copied, it results in effecting an entire copying-back for other data of the other unit pages which are not to be copied while sharing a wordline with the partial unit pages.
As the conventional memory controllers have been still designed to manage the data in the unit of 512 bytes although a unit page of flash memories is being enlarged up to 2K bytes over the 512 bytes, it needs to consider more efficient copy-back features.